Conventionally, in a liquid crystal display device employing an a-Si TFT liquid crystal panel (a liquid crystal panel that uses amorphous silicon for semiconductor layers of thin film transistors), because of the relatively small mobility of the amorphous silicon, a gate driver for driving gate bus lines (scanning signal lines) has been provided as an IC (Integrated Circuit) chip in a peripheral portion of a substrate that constitutes the panel. However, in recent years, a technique to form the gate driver directly on the substrate has been employed so as to achieve a reduction in device size, a lower cost, and the like. Such a gate driver is referred to as a “monolithic gate driver” or the like. Also, a panel provided with the monolithic gate driver is referred to as a “gate driver monolithic panel” or the like.
FIG. 11 is a block diagram showing an example of a configuration of a gate driver (monolithic gate driver) in a liquid crystal display device employing a gate driver monolithic panel. As shown in FIG. 11, the gate driver includes a shift register 400 made of a plurality of stages (disposed as many as the number of the gate bus lines). The respective stages of the shift register 400 are bistable circuits SR that are in one of two states (first state and second state) at each point in time and that output signals that indicate the above-mentioned state as scanning signals GOUT, respectively. That is, the shift register 400 is made of a plurality of bistable circuits SR. Each of the bistable circuits SR includes input terminals for receiving two-phase clock signals CKA (hereinafter referred to as “first clock”) and CKB (hereinafter referred to as “second clock”), respectively, an input terminal for receiving a low-level supply voltage VSS, an input terminal for receiving a clear signal CLR, an input terminal for receiving a set signal SET, an input terminal for receiving a reset signal RESET, and an output terminal for outputting the scanning signal GOUT. The scanning signals GOUT that are output from the respective stages (bistable circuits) are provided to corresponding gate bus lines GL, respectively. The scanning signals GOUT are also provided to the subsequent stages as the set signals SET, and the preceding stages as the reset signals RESET, respectively. A region where the bistable circuits SR constituting the shift register 400 are formed will be referred to as a “driver circuit region” below.
In FIG. 11, to the left of the driver circuit region, a main wiring line (trunk wiring line) for a gate start pulse signal GSP that is to be provided as the set signal SET to the bistable circuit SR in the first stage, a main wiring line for the low-level supply voltages VSS, a main wiring line for first gate clock signals CLK1 that are to be provided as the first clock CKA or the second clock CKB to the respective bistable circuits SR, a main wiring line for second gate clock signals CLK2 that are to be provided as the first clock CKA or the second clock CKB to the respective bistable circuits SR, and a main wiring line for clear signals CLR are formed. A region including the above-mentioned signal wiring lines for transmitting signals that drive the shift register 400 to perform a shift operation will be referred to as a “driving signal main wiring region” below. In FIG. 11, to the right of the driver circuit region, a display section for displaying images is disposed. In the display section, a pixel circuit including the gate bus lines GL, auxiliary capacitance wiring lines CSL, and the like is formed. The display section may also be referred to as a “display region” below. Between the driver circuit region and the display region, an auxiliary capacitance main wiring line CSML is formed to transmit voltage signals that are to be applied to the respective auxiliary capacitance wiring lines CSL disposed in the display section.
FIG. 12 is a circuit diagram showing an example of a configuration of one stage of the shift register 400 constituting a monolithic gate driver, that is, a configuration of the bistable circuit SR. As shown in FIG. 12, the bistable circuit includes five thin film transistors (TFTs) T41, T42, T43, T44, and T45, and a capacitor Cap. This bistable circuit also includes an input terminal for the low-level supply voltage VSS, five input terminals 41 to 45, and one output terminal (output node) 46. The source terminal of the thin film transistor T41, the drain terminal of the thin film transistor T42, and the gate terminal of the thin film transistor T43 are connected with each other. For convenience, a region (wiring line) where they are connected with each other is referred to as “netA.” In the thin film transistor T41, the gate terminal and the drain terminal are connected to the input terminal 41 (that is, a diode-connected transistor), and the source terminal is connected to netA. In the thin film transistor T42, the gate terminal is connected to the input terminal 42, the drain terminal is connected to netA, and the source terminal is connected to the supply voltage VSS. In the thin film transistor T43, the gate terminal is connected to netA, the drain terminal is connected to the input terminal 43, and the source terminal is connected to the output terminal 46. In the thin film transistor T44, the gate terminal is connected to the input terminal 44, the drain terminal is connected to the output terminal 46, and the source terminal is connected to the supply voltage VSS. In the thin film transistor T45, the gate terminal is connected to the input terminal 45, the drain terminal is connected to the output terminal 46, and the source terminal is connected to the supply voltage VSS. In the capacitor Cap, one end is connected to netA and the other end is connected to the output terminal 46.
Among the above-mentioned five thin film transistors, the thin film transistor T43 functions as an output transistor in this bistable circuit. An output transistor is a transistor that has one of the conductive terminals (source terminal in this case) connected to the output terminal in the bistable circuit and that is used to control a potential of the scanning signal by changing a potential of the control terminal of the transistor (gate terminal in this case).
Next, with reference to FIGS. 12 and 13, operations of the respective stages (bistable circuits) of the shift register 400 will be explained. The input terminal 43 is provided with the first clock CKA that is increased to a higher level in every other horizontal scanning period. The input terminal 44 is provided with the second clock CKB that is 180-degree out of phase with the first clock CKA. During the period prior to a point t0, the potential of netA and the potential of the scanning single GOUT (output terminal 46) stay at a low level.
At the point t0, a pulse of the set signal SET is applied to the input terminal 41. The point t0 is the time when the gate bus line GL connected to the preceding stage is turned to the selected state. Because the thin film transistor T41 is a diode-connected transistor as shown in FIG. 12, the thin film transistor T41 is turned to the ON state by the pulse of the set signal SET, thereby charging the capacitor Cap. This raises the potential of netA from a low level to a high level, and therefore turns the thin film transistor T43 to the ON state. During the period between t0 and t1, the first clock CKA stays at a low level. Therefore, during this period, the scanning signal GOUT is maintained at a low level. Also, during this period, the reset signal RESET stays at a low level, thereby maintaining the OFF state of the thin film transistor T42. This prevents the potential of netA from lowering during this period.
At the point t1, the first clock CKA rises to a high level from a low level. Because the thin film transistor T43 is in the ON state at this time, the potential of the output terminal 46 increases in accordance with the increase in the potential of the input terminal 43. The capacitor Cap is formed between netA and the output terminal 46 as shown in FIG. 12, and therefore, with the increase in the potential of the output terminal 46, the potential of netA is also increased (netA is bootstrapped). As a result, a high voltage is applied to the gate terminal of the thin film transistor T43, causing the potential of the scanning signal GOUT to rise to the same level as the high-level potential of the first clock CKA. This makes the gate bus line GL connected to the output terminal 46 of this bistable circuit turn to a selected state. During the period between t1 and t2, the second clock CKB and the clear signal CLR stay at a low level. This maintains the OFF state of the thin film transistors T44 and T45, and therefore, the potential of the scanning signal GOUT is not lowered during this period.
At the point t2, the first clock CKA lowers to a low level from a high level. This causes the potential of the input terminal 43 and the potential of the output terminal 46 to drop, which also lowers the potential of netA through the capacitor Cap. Also, at the point t2, a pulse of the reset signal RESET is applied to the input terminal 42, causing the thin film transistor T42 to turn to the ON state. As a result, the potential of netA is changed from a high level to a low level. Further, at the point t2, the second clock CKB is increased to a high level from a low level, causing the thin film transistor T44 to turn to the ON state. As a result, the potential of the output terminal 46, which is the potential of the scanning signal GOUT, lowers to a low level.
The scanning signals GOUT that are output from the respective stages (bistable circuits) in the manner described above are provided to the subsequent stages, respectively, as set signals as shown in FIG. 11. This turns the plurality of gate bus lines GL disposed in the display section to the selected state sequentially, one line for every horizontal scanning period. The clear signal CLR is increased to a high level at the start of the operation of this liquid crystal display device, at the start of each vertical scanning period, or the like. By the clear signal CLR reaching a high level, in all bistable circuits, the thin film transistors T45 are turned to the ON state, causing the potential of the output terminals 46, which is the potential of the scanning signals GOUT, to drop to a low level.
Here, to take a close look at the configuration of the bistable circuit shown in FIG. 12, the capacitor Cap is formed between netA and the output terminal 46, that is, between the gate and the source of thin film transistor T43. The capacitor Cap functions as a bootstrap capacitor for increasing the potential of netA with the increase in the potential of the output terminal 46. As described above, the monolithic gate driver is configured to have the bootstrap capacitor so that a higher potential than the supply potential can be generated, and the output transistor (the thin film transistor T43 in FIG. 12) can be switched from the OFF state to the ON state in a short period of time, thereby minimizing an output loss.
In relation to the present invention, the following related art documents are known. Japanese Patent Application Laid-Open Publication No. 2005-50502 discloses a configuration of a shift register for a monolithic gate driver that uses a bootstrap capacitor. Published Patent Application, Japanese Translation of PCT International Application No. 2005-527856 discloses a layout diagram of a monolithic gate driver.